Digital Electronics Concept List

This file contains 250 concepts for the Digital Electronics learning graph. Each concept is numbered with a unique ConceptID for use in the dependency graph.

Concepts

Binary Number System
Decimal to Binary Conversion
Binary to Decimal Conversion
Hexadecimal Numbers
Hex to Binary Conversion
Octal Numbers
Binary Addition
Binary Subtraction
Two's Complement
Signed Binary Numbers
Overflow Detection
BCD Encoding
Gray Code
Weighted Codes
Boolean Variable
Boolean Constant
Boolean Expression
Boolean Function
Truth Table
AND Operation
OR Operation
NOT Operation
Boolean Algebra
Identity Law
Null Law
Idempotent Law
Complement Law
Commutative Law
Associative Law
Distributive Law
Absorption Law
De Morgan's Theorem
Dual Expression
Consensus Theorem
Boolean Proof Technique
Logic Gate
AND Gate
OR Gate
NOT Gate
Buffer Gate
NAND Gate
NOR Gate
XOR Gate
XNOR Gate
Gate Symbol
IEEE Gate Symbols
Functional Completeness
Universal Gate
NAND-Only Design
NOR-Only Design
Gate Delay
Propagation Delay
Rise Time
Fall Time
Fan-In
Fan-Out
Logic Levels
Noise Margin
Voltage Threshold
Logic Family
TTL Logic
CMOS Logic
Digital Signal
Analog vs Digital
Signal Integrity
Combinational Logic
Sequential Logic
Gate-Level Design
Boolean to Gates Mapping
Multi-Level Logic
Two-Level Logic
Sum of Products
Product of Sums
Minterm
Maxterm
Canonical Form
Standard Form
Minimal Form
Logic Minimization
Algebraic Simplification
Factoring
Common Term Extraction
Karnaugh Map
K-Map 2 Variable
K-Map 3 Variable
K-Map 4 Variable
K-Map Grouping Rules
Adjacent Cells
Don't Care Condition
Prime Implicant
Essential Prime Implicant
Implicant Cover
Minimal SOP
Minimal POS
Quine-McCluskey Method
Hazard
Static Hazard
Dynamic Hazard
Hazard-Free Design
Multiplexer
MUX 2-to-1
MUX 4-to-1
MUX 8-to-1
MUX Tree
MUX as Logic Function
Demultiplexer
DEMUX 1-to-4
Encoder
Decoder
2-to-4 Decoder
3-to-8 Decoder
Decoder Enable
Priority Encoder
7-Segment Display
7-Segment Decoder
Binary Comparator
Magnitude Comparator
Equality Comparator
Half Adder
Full Adder
Carry Bit
Sum Bit
Ripple Carry Adder
Carry Propagation Delay
Carry Lookahead Concept
Adder Subtractor
Overflow in Addition
ALU Concept
Parity Bit
Parity Generator
Parity Checker
Error Detection
Tri-State Buffer
Bus Architecture
Memory Element
State Concept
Feedback Loop
Bistable Element
SR Latch
SR Latch Truth Table
Invalid State Problem
Gated SR Latch
D Latch
Level Sensitive
Transparent Latch
Latch Timing Problem
Race Condition
Clock Signal
Clock Edge
Rising Edge
Falling Edge
Clock Period
Clock Frequency
Duty Cycle
D Flip-Flop
Edge Triggered
Positive Edge Triggered
Negative Edge Triggered
Master-Slave Flip-Flop
JK Flip-Flop
JK Toggle Mode
T Flip-Flop
Flip-Flop Symbol
Preset Input
Clear Input
Asynchronous Reset
Synchronous Reset
Setup Time
Hold Time
Clock-to-Q Delay
Timing Diagram
Timing Constraint
Timing Violation
Metastability
MTBF Concept
Synchronous System
Asynchronous Input
Synchronizer Circuit
Double Flop Synchronizer
Finite State Machine
FSM State
State Transition
Current State
Next State
Next State Logic
Output Logic
Moore Machine
Moore Output
Mealy Machine
Mealy Output
State Diagram
State Diagram Notation
State Table
State Encoding
Binary Encoding
One-Hot Encoding
Gray Code Encoding
State Assignment
State Minimization
Next State Equation
Output Equation
FSM Design Process
FSM Verification
Sequence Detector
Pattern Recognition FSM
Overlapping Detection
Non-Overlapping Detection
Traffic Light Controller
Vending Machine FSM
Counter
Up Counter
Down Counter
Up-Down Counter
Mod-N Counter
Binary Counter
BCD Counter
Decade Counter
Ring Counter
Johnson Counter
Counter State Diagram
Counter Overflow
Register
Parallel Load Register
Shift Register
Serial In Serial Out
Serial In Parallel Out
Parallel In Serial Out
Parallel In Parallel Out
Bidirectional Shift
Universal Shift Register
Enable Signal
Load Signal
Clear Signal
Register File
Datapath Concept
Control Unit
Register Transfer Level
RTL Notation
Verilog HDL
HDL vs Programming
Module Definition
Port Declaration
Input Port
Output Port
Inout Port
Wire Data Type
Reg Data Type
Parameter
Assign Statement
Continuous Assignment
Always Block
Sensitivity List
Blocking Assignment
Non-Blocking Assignment
If-Else in Verilog
Case Statement
Combinational Always
Sequential Always
Posedge Keyword
Negedge Keyword
Initial Block
Structural Modeling
Behavioral Modeling
Gate-Level Verilog
RTL Verilog
Module Instantiation
Hierarchical Design
Testbench
Stimulus Generation
Clock Generation
Test Vector
Self-Checking Testbench
Simulation
Simulation Time
Waveform Viewer
Debugging Waveforms
Synthesis
Synthesizable Code
Non-Synthesizable Code
FPGA Architecture
FPGA LUT
FPGA Flip-Flop
FPGA Routing
FPGA Implementation
Pin Assignment
Breadboard Prototyping
Logic Probe
Logic Analyzer
LED Indicator
Switch Input
Debouncing
Design Verification
Functional Verification
Timing Verification
Hardware-Software Boundary
Abstraction Levels
Design Hierarchy
Design Reuse
Design Documentation
Digital System Design