Taxonomy Distribution Report

Overview

• Total Concepts: 300
• Number of Taxonomies: 11
• Average Concepts per Taxonomy: 27.3

Distribution Summary

Category	TaxonomyID	Count	Percentage	Status
Building Blocks	BLOCKS	35	11.7%	✅
Combinational Logic	COMB	34	11.3%	✅
Verification & Lab	VERIFY	33	11.0%	✅
Logic Gates	GATES	30	10.0%	✅
Finite State Machines	FSM	30	10.0%	✅
Registers & Counters	REG	29	9.7%	✅
Verilog HDL	HDL	29	9.7%	✅
Flip-Flops	FLIPFLOP	25	8.3%	✅
Boolean Algebra	BOOL	21	7.0%	✅
Sequential Basics	SEQ	20	6.7%	✅
Number Systems	NUMSYS	14	4.7%	✅

Visual Distribution

BLOCKS █████  35 ( 11.7%)
COMB   █████  34 ( 11.3%)
VERIFY █████  33 ( 11.0%)
GATES  █████  30 ( 10.0%)
FSM    █████  30 ( 10.0%)
REG    ████  29 (  9.7%)
HDL    ████  29 (  9.7%)
FLIPFLOP ████  25 (  8.3%)
BOOL   ███  21 (  7.0%)
SEQ    ███  20 (  6.7%)
NUMSYS ██  14 (  4.7%)

Balance Analysis

✅ No Over-Represented Categories

All categories are under the 30% threshold. Good balance!

Category Details

Building Blocks (BLOCKS)

Count: 35 concepts (11.7%)

Concepts:

• 1. Multiplexer
• 1. MUX 2-to-1
• 1. MUX 4-to-1
• 1. MUX 8-to-1
• 1. MUX Tree
• 1. MUX as Logic Function
• 1. Demultiplexer
• 1. DEMUX 1-to-4
• 1. Encoder
• 1. Decoder
• 1. 2-to-4 Decoder
• 1. 3-to-8 Decoder
• 1. Decoder Enable
• 1. Priority Encoder
• 1. 7-Segment Display
• ...and 20 more

Combinational Logic (COMB)

Count: 34 concepts (11.3%)

Concepts:

• 1. Combinational Logic
• 1. Sequential Logic
• 1. Gate-Level Design
• 1. Boolean to Gates Mapping
• 1. Multi-Level Logic
• 1. Two-Level Logic
• 1. Sum of Products
• 1. Product of Sums
• 1. Minterm
• 1. Maxterm
• 1. Canonical Form
• 1. Standard Form
• 1. Minimal Form
• 1. Logic Minimization
• 1. Algebraic Simplification
• ...and 19 more

Verification & Lab (VERIFY)

Count: 33 concepts (11.0%)

Concepts:

• 1. Testbench
• 1. Stimulus Generation
• 1. Clock Generation
• 1. Test Vector
• 1. Self-Checking Testbench
• 1. Simulation
• 1. Simulation Time
• 1. Waveform Viewer
• 1. Debugging Waveforms
• 1. Synthesis
• 1. Synthesizable Code
• 1. Non-Synthesizable Code
• 1. FPGA Architecture
• 1. FPGA LUT
• 1. FPGA Flip-Flop
• ...and 18 more

Logic Gates (GATES)

Count: 30 concepts (10.0%)

Concepts:

• 1. Logic Gate
• 1. AND Gate
• 1. OR Gate
• 1. NOT Gate
• 1. Buffer Gate
• 1. NAND Gate
• 1. NOR Gate
• 1. XOR Gate
• 1. XNOR Gate
• 1. Gate Symbol
• 1. IEEE Gate Symbols
• 1. Functional Completeness
• 1. Universal Gate
• 1. NAND-Only Design
• 1. NOR-Only Design
• ...and 15 more

Finite State Machines (FSM)

Count: 30 concepts (10.0%)

Concepts:

• 1. Finite State Machine
• 1. FSM State
• 1. State Transition
• 1. Current State
• 1. Next State
• 1. Next State Logic
• 1. Output Logic
• 1. Moore Machine
• 1. Moore Output
• 1. Mealy Machine
• 1. Mealy Output
• 1. State Diagram
• 1. State Diagram Notation
• 1. State Table
• 1. State Encoding
• ...and 15 more

Registers & Counters (REG)

Count: 29 concepts (9.7%)

Concepts:

• 1. Counter
• 1. Up Counter
• 1. Down Counter
• 1. Up-Down Counter
• 1. Mod-N Counter
• 1. Binary Counter
• 1. BCD Counter
• 1. Decade Counter
• 1. Ring Counter
• 1. Johnson Counter
• 1. Counter State Diagram
• 1. Counter Overflow
• 1. Register
• 1. Parallel Load Register
• 1. Shift Register
• ...and 14 more

Verilog HDL (HDL)

Count: 29 concepts (9.7%)

Concepts:

• 1. Verilog HDL
• 1. HDL vs Programming
• 1. Module Definition
• 1. Port Declaration
• 1. Input Port
• 1. Output Port
• 1. Inout Port
• 1. Wire Data Type
• 1. Reg Data Type
• 1. Parameter
• 1. Assign Statement
• 1. Continuous Assignment
• 1. Always Block
• 1. Sensitivity List
• 1. Blocking Assignment
• ...and 14 more

Flip-Flops (FLIPFLOP)

Count: 25 concepts (8.3%)

Concepts:

• 1. D Flip-Flop
• 1. Edge Triggered
• 1. Positive Edge Triggered
• 1. Negative Edge Triggered
• 1. Master-Slave Flip-Flop
• 1. JK Flip-Flop
• 1. JK Toggle Mode
• 1. T Flip-Flop
• 1. Flip-Flop Symbol
• 1. Preset Input
• 1. Clear Input
• 1. Asynchronous Reset
• 1. Synchronous Reset
• 1. Setup Time
• 1. Hold Time
• ...and 10 more

Boolean Algebra (BOOL)

Count: 21 concepts (7.0%)

Concepts:

• 1. Boolean Variable
• 1. Boolean Constant
• 1. Boolean Expression
• 1. Boolean Function
• 1. Truth Table
• 1. AND Operation
• 1. OR Operation
• 1. NOT Operation
• 1. Boolean Algebra
• 1. Identity Law
• 1. Null Law
• 1. Idempotent Law
• 1. Complement Law
• 1. Commutative Law
• 1. Associative Law
• ...and 6 more

Sequential Basics (SEQ)

Count: 20 concepts (6.7%)

Concepts:

• 1. Memory Element
• 1. State Concept
• 1. Feedback Loop
• 1. Bistable Element
• 1. SR Latch
• 1. SR Latch Truth Table
• 1. Invalid State Problem
• 1. Gated SR Latch
• 1. D Latch
• 1. Level Sensitive
• 1. Transparent Latch
• 1. Latch Timing Problem
• 1. Race Condition
• 1. Clock Signal
• 1. Clock Edge
• ...and 5 more

Number Systems (NUMSYS)

Count: 14 concepts (4.7%)

Concepts:

• 1. Binary Number System
• 1. Decimal to Binary Conversion
• 1. Binary to Decimal Conversion
• 1. Hexadecimal Numbers
• 1. Hex to Binary Conversion
• 1. Octal Numbers
• 1. Binary Addition
• 1. Binary Subtraction
• 1. Two's Complement
• 1. Signed Binary Numbers
• 1. Overflow Detection
• 1. BCD Encoding
• 1. Gray Code
• 1. Weighted Codes

Recommendations

• ✅ Excellent balance: Categories are evenly distributed (spread: 7.0%)
• ✅ MISC category minimal: Good categorization specificity

Educational Use Recommendations

• Use taxonomy categories for color-coding in graph visualizations
• Design curriculum modules based on taxonomy groupings
• Create filtered views for focused learning paths
• Use categories for assessment organization
• Enable navigation by topic area in interactive tools

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Report generated by learning-graph-reports/taxonomy_distribution.py