Chapter Metrics
Generated by: Book Metrics Python Program v0.08
Generated on: June 03, 2026 at 12:10 PM
This file contains chapter-by-chapter metrics for student-facing content.
| Chapter | Name | Sections | Diagrams | Equations | Words | Links | Quiz | Refs |
|---|---|---|---|---|---|---|---|---|
| 1 | Number Systems and Binary Arithmetic | 41 | 8 | 16 | 6,473 | 6 | 10 | 5 |
| 2 | Boolean Algebra Fundamentals | 36 | 5 | 0 | 6,456 | 6 | 10 | 5 |
| 3 | Logic Gates and Digital Signal Properties | 38 | 17 | 0 | 9,025 | 6 | 10 | 5 |
| 4 | Combinational Logic Design Fundamentals | 38 | 8 | 0 | 6,963 | 7 | 10 | 5 |
| 5 | Logic Minimization and Karnaugh Maps | 50 | 8 | 0 | 7,770 | 6 | 10 | 5 |
| 6 | Combinational Building Blocks | 46 | 16 | 0 | 9,977 | 7 | 10 | 5 |
| 7 | Introduction to Sequential Logic | 28 | 10 | 0 | 8,750 | 7 | 10 | 5 |
| 8 | Flip-Flops and Timing | 33 | 9 | 0 | 9,760 | 6 | 10 | 5 |
| 9 | Finite State Machine Fundamentals | 29 | 9 | 0 | 9,146 | 8 | 10 | 5 |
| 10 | FSM Design and Applications | 53 | 8 | 0 | 8,238 | 6 | 10 | 5 |
| 11 | Registers, Counters, and Datapath | 35 | 9 | 0 | 8,322 | 7 | 10 | 5 |
| 12 | Verilog HDL Fundamentals | 24 | 6 | 1 | 6,424 | 8 | 10 | 5 |
| 13 | Verilog Behavioral and Structural Modeling | 21 | 9 | 0 | 5,920 | 7 | 10 | 5 |
| 14 | Testbenches and Simulation | 19 | 8 | 65 | 5,666 | 8 | 10 | 5 |
| 15 | FPGA Implementation and Laboratory Skills | 23 | 8 | 0 | 7,065 | 10 | 10 | 5 |
Metrics Explanation
- Chapter: Chapter number (leading zeros removed)
- Name: Chapter title from index.md
- Sections: Count of H2 and H3 headers in chapter markdown files
- Diagrams: Count of H4 headers starting with '#### Diagram:'
- Equations: LaTeX expressions using $ and $$ delimiters
- Words: Word count across all markdown files in the chapter
- Links: Markdown-formatted links
[text](url) - Quiz: Number of quiz questions in the chapter's quiz.md (0 if none)
- Refs: Number of references in the chapter's references.md (0 if none)