Short-Channel Effects, CMOS, and Advanced FET Structures
Summary
As MOSFET channel lengths have shrunk below 100 nm, short-channel effects degrade the clean long-channel behavior derived in Chapter 15. This chapter analyzes the principal degradation mechanisms: drain-induced barrier lowering (DIBL), punch-through, velocity saturation, carrier heating, hot-carrier injection into the gate oxide, and oxide interface degradation. CMOS technology pairs N- and P-channel MOSFETs for logic; the CMOS inverter, static and dynamic power dissipation, and complementary operation are covered. Modern FET architectures that restore electrostatic control at short gate lengths are then surveyed: FinFET, gate-all-around (GAA) nanowire transistors, SOI MOSFETs (fully and partially depleted), and multi-gate devices. The chapter closes with MOSFET scaling laws, Dennard scaling and its breakdown, and the International Roadmap for Devices and Systems (IRDS).
Concepts Covered
This chapter covers the following 26 concepts from the learning graph:
- Short-Channel Effects
- DIBL Effect
- Drain-Induced Barrier Lowering
- Punch-Through
- Velocity Saturation MOSFET
- Carrier Heating MOSFET
- Hot Carrier Injection
- Oxide Interface Degradation
- CMOS Technology
- CMOS Inverter
- NMOS Pull-Down
- PMOS Pull-Up
- Complementary Operation
- Static Power CMOS
- Dynamic Power CMOS
- FinFET Structure
- FinFET Operation
- Gate-All-Around Transistor
- SOI MOSFET
- Fully Depleted SOI
- Partially Depleted SOI
- Multi-Gate Transistor
- Nanowire Transistor
- Scaling Laws MOSFET
- Dennard Scaling
- International Roadmap Devices
Prerequisites
This chapter builds on concepts from:
- Chapter 11: P-N Junction: Equilibrium, Bias, and the Ideal Diode
- Chapter 13: Metal-Semiconductor Contacts and MOS Physics
- Chapter 15: JFET, MESFET, and Long-Channel MOSFET Fundamentals
Nova on Short-Channel Effects: What Happens When You Shrink Too Far
The long-channel MOSFET model from Chapter 15 is elegant, predictive, and accurate for gate lengths above ~500 nm. Below that, reality sends strongly worded correction memos. Drain-induced barrier lowering, punch-through, velocity saturation, hot-carrier damage — these are not academic curiosities but the physical walls that the semiconductor industry has been crash-testing since the 1990s. Today we understand the walls, and then we meet the architecture innovations (FinFET, GAA, SOI) that let engineers keep scaling despite the walls. Warning: the walls are fascinating.
16.1 Short-Channel Effects: An Overview
As channel length \(L\) decreases, the source and drain depletion regions become comparable in size to the channel length itself. The gate electrode loses exclusive control of the channel potential — the drain bias can "reach around" and lower the source-channel barrier. This general phenomenon — degraded electrostatic control at short channel lengths — encompasses several related effects.
The natural length scale that determines when short-channel effects become important is approximately:
where \(t_{\text{dep}} = \sqrt{2\varepsilon_s\phi_F/qN_A}\) is the depletion depth. Short-channel effects become severe when \(L \lesssim 5\lambda_{\text{nat}}\).
To suppress short-channel effects, industry roadmaps require reducing both \(t_{\text{ox}}\) (thinner gate dielectric) and \(t_{\text{dep}}\) (higher channel doping or geometrically confined channels) in proportion to \(L\).
16.2 Drain-Induced Barrier Lowering (DIBL)
DIBL is the reduction of the source-channel potential barrier caused by the drain electric field. In a long-channel device, the source-channel barrier is controlled entirely by \(V_{GS}\). In a short-channel device, the drain field lines penetrate the channel and lower the barrier even when \(V_{GS}\) is below threshold.
The consequence: threshold voltage decreases with increasing \(V_{DS}\).
where the DIBL coefficient (in mV/V) characterizes how strongly the drain modulates the threshold. For a well-designed device: DIBL < 50 mV/V. For a poorly-controlled short-channel device: DIBL can exceed 200 mV/V.
DIBL causes: 1. Lower threshold voltage at high drain bias → higher off-state leakage (\(I_{\text{OFF}}\)) 2. Effective subthreshold slope degradation (looks steeper in \(V_{DS}\)-adjusted plot) 3. Coupling between input (\(V_{GS}\)) and output (\(V_{DS}\)) — the drain is no longer an independent variable
The practical impact: if DIBL shifts \(V_T\) by 100 mV at \(V_{DS} = 0.8\) V, a transistor designed for 100× current ratio (ON/OFF) might achieve only 10× — leakage power increases 10-fold.
16.3 Punch-Through
Punch-through occurs when the source and drain depletion regions merge across the channel, creating a direct conductive path between source and drain that bypasses gate control entirely. The channel "punches through" with a leakage current that cannot be turned off by the gate.
The punch-through voltage for a uniformly doped channel is approximately:
where \(W_n\) and \(W_p\) are the zero-bias depletion widths from drain and source. Punch-through is suppressed by: - Increasing channel doping (reduces depletion widths) - Using halo/pocket implants (locally higher doping near source and drain edges under the gate) - Physically short source/drain junctions (shallow junctions)
Modern CMOS uses retrograde doping (lower doping at the surface to maximize mobility, higher doping deeper to suppress punch-through) and halo implants (high-dose angled implants under the gate edges) to control both phenomena.
16.4 Velocity Saturation in Short-Channel MOSFETs
In Chapter 15, saturation occurred when \(V_{DS} = V_{GS} - V_T\) (pinch-off). In short-channel devices, the average channel field \(\mathcal{E} = V_{DS}/L\) can easily exceed the critical field \(\mathcal{E}_c \approx 7\) kV/cm (Chapter 8), causing velocity saturation before pinch-off.
When velocity saturates at \(v_{\text{sat}}\), the saturation current becomes:
This changes the I-V characteristic from quadratic (\(\propto V_{OD}^2\)) to linear in overdrive (\(\propto V_{OD}\)) — a fundamental change in device behavior. The transconductance in the velocity-saturated regime:
No longer proportional to \(\sqrt{I_D}\) — it becomes independent of bias in the fully velocity-saturated regime. This means that making the transistor conduct more current (by increasing \(V_{OD}\)) doesn't proportionally increase \(g_m\) — a major change from long-channel behavior.
The effective drive current for a modern NMOS at the 5 nm node:
where \(v_{\text{inj}}\) is the carrier injection velocity at the virtual source (top of the barrier) — often comparable to or exceeding the thermal velocity. At the nanoscale, transistors operate in a quasi-ballistic regime, and the classical velocity saturation picture becomes an approximation.
16.5 CMOS Technology: Complementary N and P Channel
CMOS (Complementary MOS) pairs NMOS and PMOS transistors on the same substrate. The complementary operation enables the CMOS inverter — the fundamental logic gate — to achieve near-zero static power dissipation.
CMOS inverter operation:
- Input HIGH (\(V_{in} \approx V_{DD}\)): NMOS on (low \(V_{GS,n}\) relative to threshold), PMOS off (insufficient gate-to-source magnitude) → Output = LOW
- Input LOW (\(V_{in} \approx 0\)): NMOS off, PMOS on → Output = HIGH
In both stable states, one transistor is off — no DC path from \(V_{DD}\) to ground. Static power dissipation is essentially zero, limited only by subthreshold leakage. This property enabled scaling to billions of transistors while keeping power manageable.
Dynamic power dissipation: Occurs during switching, when the output capacitance \(C_L\) is charged/discharged:
where \(\alpha\) is the activity factor (fraction of transitions that occur per clock cycle, typically 0.1–0.3), and \(f\) is the clock frequency. This equation explains the power crisis in modern processors:
- Increasing \(f\) linearly increases dynamic power
- Reducing \(V_{DD}\) quadratically reduces dynamic power — the primary lever for power reduction
- \(C_L\) decreases with scaling — the historical benefit that kept energy per operation declining
Static (leakage) power has grown with device scaling:
As \(L\) decreases, \(I_{\text{OFF}}\) grows (DIBL, reduced \(V_T\)), and \(N_{\text{transistors}}\) grows with Moore's Law. At 3 nm nodes, leakage power in idle mode rivals dynamic power in activity — a fundamental challenge that power gating, multi-threshold CMOS, and clock gating address.
Nova Tips: V_DD Reduction Is the Power Engineer's Best Weapon
Every factor-of-2 reduction in supply voltage (\(V_{DD}\)) reduces dynamic power by 4× (quadratic dependence). This is why the industry has relentlessly pushed \(V_{DD}\) from 5 V (0.8 μm era) to 3.3 V to 1.8 V to 1.0 V to 0.7–0.8 V at 5 nm. The constraint: if you reduce \(V_{DD}\), you must also reduce \(V_T\), or the ON/OFF ratio degrades. But lower \(V_T\) means higher subthreshold leakage. This \(V_{DD}\)-\(V_T\) dance — bounded below by the 60 mV/decade subthreshold slope limit — is the reason Dennard scaling eventually broke down.
16.6 Dennard Scaling and Its Breakdown
Dennard scaling (1974) defined the ideal MOSFET scaling rules: if all dimensions (L, W, \(t_{\text{ox}}\)) and voltages (\(V_{DD}\), \(V_T\)) are scaled by 1/k, transistor density increases by \(k^2\) while power density stays constant and performance improves by \(k\). For 25 years (roughly 1975–2005), the industry tracked Dennard scaling with remarkable fidelity.
Dennard scaling assumed: 1. Electric field \(\mathcal{E} = V_{DD}/L\) stays constant → no increase in field-dependent reliability issues 2. Power density \(P/A \propto \mathcal{E}^2\sigma\) stays constant → chip power stays manageable 3. Threshold voltage scales with \(V_{DD}\)
Breakdown of Dennard scaling (~2005): The minimum practical threshold voltage (set by leakage constraints) stopped scaling around 0.2–0.3 V. Subthreshold slope (60 mV/decade fundamental limit) prevented further \(V_T\) reduction without unacceptable leakage. With \(V_T\) fixed and \(L\) continuing to decrease, \(V_{DD}\) couldn't scale proportionally. Power density started increasing. By 2005, clock frequencies stopped increasing (processors hit "the power wall") and the industry pivoted to multi-core architectures.
| Era | Gate Length | \(V_{DD}\) | Scaling Mode |
|---|---|---|---|
| Classic | >1 μm | 5 V | Full Dennard scaling |
| Transitional | 500–100 nm | 3.3–1.2 V | Partial voltage scaling |
| Modern | <100 nm | 1.0–0.7 V | Constant field, scaling limited |
| Current | <10 nm | 0.7–0.6 V | Performance limited by SCE, leakage |
16.7 Advanced FET Architectures
The breakdown of planar MOSFET electrostatics at short channel lengths drove the development of three-dimensional gate geometries that restore electrostatic control.
16.7.1 FinFET
A FinFET (fin field-effect transistor) uses a thin silicon fin (width ~5–8 nm) as the channel, with the gate wrapping around three sides of the fin. The fin is narrow enough that the gate controls the entire fin cross-section — dramatically reducing the natural length scale \(\lambda_{\text{nat}}\):
With \(t_{\text{fin}} = 6\) nm and \(t_{\text{ox}} = 1\) nm (EOT): \(\lambda_{\text{nat}} \approx 2\) nm. This allows gate lengths of 10–30 nm while maintaining good electrostatic control.
Intel introduced the first commercial FinFET at 22 nm node in 2011. By 2023, all leading-edge processors (Apple M-series, Intel Core Gen 13, AMD Zen 4) use FinFET or GAA at 3–5 nm nodes. The fin geometry increases drive current per footprint area but introduces quantization of the device width (width = integer number of fins × fin pitch), complicating analog circuit design.
16.7.2 Gate-All-Around (GAA) Nanowire Transistors
GAA transistors wrap the gate around all four sides of a nanowire channel, providing maximum electrostatic control. The natural length scale is:
For a 5 nm diameter silicon nanowire: \(\lambda_{\text{nat}} \approx 1.5\) nm — even better than FinFET.
Samsung and TSMC introduced nanosheet GAA transistors at the 3 nm node (2023). Multiple stacked nanosheets (horizontally oriented, also called "nanoribbons") replace a single wire, recovering current drive capability while maintaining superior electrostatic control. This architecture is expected to enable scaling to 1–2 nm equivalent nodes through the late 2020s.
16.7.3 SOI MOSFETs
Silicon-on-insulator (SOI) places a thin silicon layer on a buried oxide (BOX), isolating it from the substrate. The isolation eliminates bulk punch-through and reduces junction capacitances.
Fully depleted SOI (FDSOI): The silicon body is thin enough (~5–15 nm) that it is completely depleted even with no gate bias. Benefits: very low \(\lambda_{\text{nat}}\) (good short-channel control), no body effect variability, and the buried oxide allows back-gate biasing for dynamic \(V_T\) adjustment. ST Microelectronics' 28 nm and 22 nm FDSOI processes power IoT and automotive chips with excellent power efficiency.
Partially depleted SOI (PDSOI): Thicker silicon body (~100 nm), partially depleted. The floating body creates anomalous effects (kink effect, floating-body charging) but also enables specific circuit tricks (DRAM-like memory using floating body).
16.8 The International Roadmap for Devices and Systems (IRDS)
The IRDS (formerly ITRS) is the semiconductor industry's collective technology roadmap, updated annually by experts from TSMC, Intel, Samsung, IBM, and academia. It projects required device performance, process parameters, and emerging research directions for the next 15 years.
Key IRDS projections for near-term nodes (as of 2024):
| Node Name | Physical Gate Length | \(V_{DD}\) | Architecture | Target Year |
|---|---|---|---|---|
| 3 nm | 12–15 nm | 0.75 V | FinFET / GAA | 2023–2024 |
| 2 nm | 9–12 nm | 0.70 V | GAA nanosheet | 2025 |
| 1.4 nm | 6–9 nm | 0.65 V | GAA / CFET | 2027 |
| 1 nm | 5–7 nm | 0.60 V | CFET / 3D ICs | 2029+ |
CFET (complementary FET) stacks NMOS and PMOS vertically in the same footprint — doubling logic density by 3D stacking within a single cell. 3D ICs (chiplets bonded face-to-face) further increase density while relaxing lithography requirements.
The IRDS increasingly acknowledges that performance scaling is slowing but density scaling continues through architecture innovation (3D, heterogeneous integration) rather than pure lithographic shrink.
Nova Celebrates: You Now Understand the World's Most Complex Manufacturing
From Fermi-Dirac statistics to FinFET short-channel effects to the IRDS roadmap — you've now traversed the full span of modern semiconductor device physics. The same equations for electron transport in a crystal that Bloch wrote in 1928 govern the behavior of 2 nm GAA transistors being manufactured in 2025. The physics is timeless; the engineering is breathtaking. Chapters 17–22 cover optoelectronics, compound semiconductors, fabrication, and characterization — the broader world that the MOSFET enabled. Time to jump bands (one last time)!
#### MicroSim: MOSFET Scaling Simulator
sim-id: mosfet-scaling-simulator
Library: p5.js
Status: specification
Description: Interactive visualization of MOSFET scaling showing how key parameters change with gate length from 1 μm to 5 nm. Three linked panels: (1) Cross-section of the transistor updating from planar to FinFET to GAA geometry; (2) Key parameters vs. L (DIBL coefficient, subthreshold slope degradation, \(V_T\) roll-off); (3) Power-performance tradeoff (dynamic power, leakage power, clock frequency) vs. technology node. Dennard scaling region and post-Dennard region shaded differently.
Controls: - Slider: Gate length (5 nm to 1 μm) - Dropdown: Architecture (Planar / FinFET / FDSOI / GAA) - Slider: Supply voltage \(V_{DD}\) (0.5–1.5 V) - Checkbox: Show Dennard scaling reference line
Key Learning Objectives: - L2 (Understand): Identify which short-channel effects dominate at each technology node - L3 (Apply): Calculate power dissipation for a given frequency and activity factor - L4 (Analyze): Explain why FinFET provides better electrostatic control than planar MOSFET - L5 (Evaluate): Compare trade-offs between different advanced FET architectures
Summary
This chapter covered the physics and architecture challenges of scaled MOSFETs:
- DIBL: Drain field lowers threshold voltage; DIBL coefficient < 50 mV/V for good devices
- Punch-through: Source-drain depletion regions merge; suppressed by halo implants and retrograde doping
- Velocity saturation: At short channels, \(I_D^{\text{sat}} \propto V_{OD}\) (linear) not \(V_{OD}^2\); \(g_m \approx W C_{\text{ox}} v_{\text{sat}}\)
- CMOS inverter: Near-zero static power (one transistor always off); dynamic power \(= \alpha C_L V_{DD}^2 f\)
- Dennard scaling: Constant power density for 1975–2005; broken by \(V_T\) scaling limits and leakage growth
- FinFET/GAA/SOI: 3D geometries restore electrostatic control by reducing \(\lambda_{\text{nat}}\); industry standard at ≤22 nm nodes
- IRDS projects further scaling via stacked GAA, CFET, and 3D heterogeneous integration